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-- turn off superfluous VHDL processor warnings 
-- altera message_level Level1 
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 

library altera;
use altera.altera_europa_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity AVALON is 
        port (
              -- inputs:
                 signal acknowledge : IN STD_LOGIC;
                 signal avalon_address : IN STD_LOGIC;
                 signal avalon_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal avalon_chipselect : IN STD_LOGIC;
                 signal avalon_read : IN STD_LOGIC;
                 signal avalon_write : IN STD_LOGIC;
                 signal avalon_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal irq : IN STD_LOGIC;
                 signal read_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal reset : IN STD_LOGIC;

              -- outputs:
                 signal address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal avalon_irq : OUT STD_LOGIC;
                 signal avalon_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal avalon_waitrequest : OUT STD_LOGIC;
                 signal bus_enable : OUT STD_LOGIC;
                 signal byte_enable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal rw : OUT STD_LOGIC;
                 signal write_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );
end entity AVALON;


architecture europa of AVALON is
component Altera_UP_Avalon_to_External_Bus_Bridge is 
           generic (
                    ADDR_BITS : integer := 18;
                    ADDR_LOW : integer := 1;
                    BYTE_EN_BITS : integer := 2;
                    DATA_BITS : integer := 16
                    );
           port (
                 -- inputs:
                    signal acknowledge : IN STD_LOGIC;
                    signal avalon_address : IN STD_LOGIC;
                    signal avalon_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal avalon_chipselect : IN STD_LOGIC;
                    signal avalon_read : IN STD_LOGIC;
                    signal avalon_write : IN STD_LOGIC;
                    signal avalon_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal irq : IN STD_LOGIC;
                    signal read_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal reset : IN STD_LOGIC;

                 -- outputs:
                    signal address : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal avalon_irq : OUT STD_LOGIC;
                    signal avalon_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal avalon_waitrequest : OUT STD_LOGIC;
                    signal bus_enable : OUT STD_LOGIC;
                    signal byte_enable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                    signal rw : OUT STD_LOGIC;
                    signal write_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component Altera_UP_Avalon_to_External_Bus_Bridge;

                signal internal_address :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal internal_avalon_irq :  STD_LOGIC;
                signal internal_avalon_readdata :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal internal_avalon_waitrequest :  STD_LOGIC;
                signal internal_bus_enable :  STD_LOGIC;
                signal internal_byte_enable :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal internal_rw :  STD_LOGIC;
                signal internal_write_data :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  --the_Altera_UP_Avalon_to_External_Bus_Bridge, which is an e_instance
  the_Altera_UP_Avalon_to_External_Bus_Bridge : Altera_UP_Avalon_to_External_Bus_Bridge
    generic map(
      ADDR_BITS => 0,
      ADDR_LOW => 2,
      BYTE_EN_BITS => 4,
      DATA_BITS => 32
    )
    port map(
      address => internal_address,
      avalon_irq => internal_avalon_irq,
      avalon_readdata => internal_avalon_readdata,
      avalon_waitrequest => internal_avalon_waitrequest,
      bus_enable => internal_bus_enable,
      byte_enable => internal_byte_enable,
      rw => internal_rw,
      write_data => internal_write_data,
      acknowledge => acknowledge,
      avalon_address => avalon_address,
      avalon_byteenable => avalon_byteenable,
      avalon_chipselect => avalon_chipselect,
      avalon_read => avalon_read,
      avalon_write => avalon_write,
      avalon_writedata => avalon_writedata,
      clk => clk,
      irq => irq,
      read_data => read_data,
      reset => reset
    );


  --vhdl renameroo for output signals
  address <= internal_address;
  --vhdl renameroo for output signals
  avalon_irq <= internal_avalon_irq;
  --vhdl renameroo for output signals
  avalon_readdata <= internal_avalon_readdata;
  --vhdl renameroo for output signals
  avalon_waitrequest <= internal_avalon_waitrequest;
  --vhdl renameroo for output signals
  bus_enable <= internal_bus_enable;
  --vhdl renameroo for output signals
  byte_enable <= internal_byte_enable;
  --vhdl renameroo for output signals
  rw <= internal_rw;
  --vhdl renameroo for output signals
  write_data <= internal_write_data;

end europa;

